Field effect transistors (FETs) employing a so-called "floating gate" along with a control gate are well known. The floating gate differs from a control gate in that it has no direct electrical connection to any external component and is surrounded by isolation on all sides. The presence of the control gate enables the device to function as a regular FET, while the floating gate collects and stores injected electrons or holes. The floating gate provides a method for changing the threshold voltage needed to pass a charge from the source to the drain. The presence of the control gate adds control to the injection of charges into and out of the floating gate, and thus enables the device to function as an electrically reprogrammable memory device.
Source-side injection flash cells or split gate flash cells are commonly used as embedded flash memories. In a split gate cell, the floating gate overlies only a portion of the channel and the control gate overlies both the floating gate and the remainder of the channel. In other words, there are two transistors in series between a source and a drain. One relatively popular flash cell employs oxidized polysilicon to create sharp points in the polysilicon in order to enhance the electric field. This in turn allows erasure at lower voltages and provides for thicker dielectric layers between the floating gate and the control gate. The commonly used process for fabricating such cells is referred to as localized oxidation of silicon (LOCOS) process over the floating gate polysilicon to form an insulator cap along with sharp points on the floating gate. The LOCOS process results in bird's beak creating the sharp points.
Nevertheless, the existing flash memory cells exhibit two major shortcomings which are high programming voltage required and non-planar cell topography due to the presence of the floating gate.
In order to inject electrons into the floating gate, either by hot electron or electron tunnelling (Fowler-Nordheim or F-N tunnelling), a high vertical electrical field must be induced. For instance, typically more than about 10 volts of voltage difference is needed between the control gate and source, drain or substrate. For example, with a prior art configuration utilizing source-side hot electron injection, the required programming voltage is 10 V. This split gate flash memory cell as shown in FIG. 1 has a floating gate on top of the silicon surface that is typical of most of the conventional structures. However, incorporating this technology into a logic application presents problems for metallization due to the topography, especially when wiring dimensions become less than 0.25 microns. Lithographic patterning and reactive ion metal etching both are quite difficult to perform on a non-planar gate surface.